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lt1952/lt1952-1 1 19521fe typical application description single switch synchronous forward controller the lt ? 1952/lt1952-1 are current mode pwm controllers optimized to control the forward converter topology, using one primary mosfet. the lt1952/lt1952-1 provide synchronous rectifer control, resulting in extremely high effciency. a programmable volt-second clamp provides a safeguard for transformer reset that prevents saturation. this allows a single mosfet on the primary side to reliably run at greater than 50% duty cycle for high mosfet, transformer and rectifer utilization. the devices include soft-start for controlled exit from shutdown and undervoltage lockout. a precision 107mv current limit threshold, independent of duty cycle, combines with soft- start to provide hiccup short-circuit protection. the lt1952 is optimized for micropower bootstrap start-up from high input voltages. the lt1952-1 allows start-up from lower input voltages. programmable slope compensation and leading edge blanking allow optimization of loop bandwidth with a wide range of inductors and mosfets. each device can be programmed over a 100khz to 500khz frequency range and the part can be synchronized to an external clock. the error amplifer is a true op amp, allowing a wide range of compensation networks. the lt1952/lt1952-1 are available in a small 16-pin ssop package. 36v to 72v input, 12v at 20a semi-regulated bus converter features applications n synchronous rectifer control for high effciency n programmable volt-second clamp n output power levels from 25w to 500w n low current start-up (lt1952: 460a; v in on/off = 14.25v/8.75v) (lt1952-1: 400a; v in on/off = 7.75v/6.5v) n true pwm soft-start n low stress short-circuit protection n precision 107mv current limit threshold n adjustable delay for synchronous timing n accurate shutdown threshold with programmable hysteresis n programmable slope compensation n programmable leading edge blanking n programmable frequency (100khz to 500khz) n synchronizable to an external clock up to 1.5 ? f osc n internal 1.23v reference n 2.5v external reference n current mode control n small 16-pin ssop package n telecommunications power supplies n industrial and distributed power n isolated and non isolated dc/dc converters v in v in t1 pa0905 supply from bias winding of t1 si7370 2 ph4840 2 l1 pa1494.242 47f 16v x5r 2 v out 12v 20a 220pf 560 t2 1952 ta01 v ref comp ss_maxdc sd_v sec fb sync gnd v in out oc i sense sout lt1952/ lt1952-1 blank delay r osc 0.1f 40k 16v 340k 13k 52.3k 40k 40k pgnd 178k 100k si7450 0.005 sync fg cg ltc3900 10f 0.1f 12v bus converter v out vs v in v in (v) 36 8 v out (v) 10 16 48 60 66 1952 ta01b 14 12 42 54 72 l , lt, ltc and ltm are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
lt1952/lt1952-1 2 19521fe pin configuration absolute maximum ratings v in (note 8) ............................................... C 0.3v to 25v sync, ss_maxdc, sd_v sec , i sense , oc .... C 0.3v to 6v comp, blank, delay ............................... C 0.3v to 3.5v fb ................................................................ C 0.3v to 3v r osc ..................................................................... C 50a v ref .................................................................... C10ma operating junction temperature range (notes 2, 5) e-, i-grades ....................................... C 40c to 125c mp-grade .......................................... C55c to 125c storage temperature range ................... C 65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 comp fb r osc sync ss_maxdc v ref sd_v sec gnd sout v in out pgnd delay oc i sense blank t jmax = 125c, q ja = 110c/w, q jc = 40c/w order information lead free finish tape and reel part marking package description temperature range lt1952egn#pbf lt1952egn#trpbf 1952 16-lead plastic ssop C 40c to 125c lt1952ign#pbf lt1952ign#trpbf 1952i 16-lead plastic ssop C 40c to 125c lt1952mpgn#pbf lt1952mpgn#trpbf 1952 16-lead plastic ssop C55c to 125c lt1952egn-1#pbf lt1952egn-1#trpbf 19521 16-lead plastic ssop C 40c to 125c lt1952ign-1#pbf lt1952ign-1#trpbf 1952i1 16-lead plastic ssop C 40c to 125c lt1952mpgn-1#pbf lt1952mpgn-1#trpbf 19521 16-lead plastic ssop C55c to 125c lead based finish tape and reel part marking package description temperature range lt1952egn lt1952egn#tr 1952 16-lead plastic ssop C 40c to 125c lt1952ign lt1952ign#tr 1952i 16-lead plastic ssop C 40c to 125c lt1952mpgn lt1952mpgn#tr 1952 16-lead plastic ssop C55c to 125c lt1952egn-1 lt1952egn-1#tr 19521 16-lead plastic ssop C 40c to 125c lt1952ign-1 lt1952ign-1#tr 1952i1 16-lead plastic ssop C 40c to 125c lt1952mpgn-1 lt1952mpgn-1#tr 19521 16-lead plastic ssop C55c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
lt1952/lt1952-1 3 19521fe parameter conditions min typ max units pwm controller operational input voltage i(v ref ) = 0a l v in off 25 v v in quiescent current i(v ref ) = 0a, i sense = oc = open 5.2 6.5 ma v in start-up current (lt1952) fb = 0v, ss_maxdc = 0v (notes 4, 9) l 460 700 a v in start-up current (lt1952-1) fb = 0v, ss_maxdc = 0v (notes 4, 9) l 400 575 a v in shutdown current sd_v sec = 0v 240 350 a sd_v sec threshold 10v < v in < 25v l 1.261 1.32 1.379 v sd_v sec (on) current sd_v sec = sd_v sec threshold + 100mv 0 a sd_v sec (off) current sd_v sec = sd_v sec threshold C 100mv 8.3 10 11.7 a v in on (lt1952) l 14.25 15.75 v v in off (lt1952) l 8.75 9.25 v v in hysteresis (lt1952) l 3.75 5.5 6.75 v v in on (lt1952-1) e-, i-grades mp-grade l l 7.75 7.75 8.13 8.3 v v v in off (lt1952-1) l 6.5 6.82 v v in hysteresis (lt1952-1) l 0.95 1.25 v v ref output voltage i(v ref ) = 0a l 2.425 2.5 2.575 v line regulation i(v ref ) = 0a, 10v < v in < 25v 1 10 mv load regulation 0a < i(v ref ) < 2.5ma 1 10 mv oscillator frequency: f osc r osc = 178k, fb = 1v, ss_maxdc = 1.84v l 165 200 240 khz minimum programmable f osc maximum programmable f osc r osc = 365k, fb = 1v r osc = 64.9k, comp = 2.5v, sd_v sec = 2.64v 80 440 100 500 120 560 khz khz sync input resistance 18 k sync switching threshold fb = 1v 1.5 2.2 v sync frequency/f osc fb = 1v (note 7) 1.25 1.5 f osc line reg fb = 1v, r osc = 178k; 10v < v in < 25v, ss_maxdc = 1.84v 0.05 0.33 %/v v rosc r osc pin voltage 1 v error amplifier fb reference voltage 10v < v in < 25v, v ol + 0.2v < comp < v oh C 0.2 l 1.201 1.226 1.250 v fb input bias current fb = fb reference voltage C75 C200 na open loop voltage gain v ol + 0.2v < comp < v oh C 0.2 65 85 db unity gain bandwidth (note 6) 3 mhz comp source current fb = 1v, comp = 1.6v C4 C9 ma comp sink current comp = 1.6v 4 10 ma comp current (disabled) fb = v ref , comp = 1.6v 18 23 28 a comp high level: v oh fb = 1v, i (comp) = C250a 2.7 3.2 v comp active threshold fb = 1v, sout duty cycle > 0 % 0.7 0.8 v the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c (note 2). comp = open, fb = 1.4v, r osc = 178k, sync = 0v, ss_maxdc = v ref , v ref = 0.1f, sd_v sec = 2v, blank = 121k, delay = 121k, i sense = 0v, oc = 0v, out = 1nf, v in = 15v, sout = open, unless otherwise specifed. electrical characteristics
lt1952/lt1952-1 4 19521fe parameter conditions min typ max units comp low level: v ol i (comp) = 250a 0.15 0.4 v current sense i sense maximum threshold comp = 2.5v, fb = 1v 197 220 243 mv i sense input current (duty cycle = 0%) i sense input current (duty cycle = 80%) comp = 2.5v, fb = 1v (note 4) comp = 2.5v, fb = 1v (note 4) C8 C35 a a oc threshold comp = 2.5v, fb = 1v 98 107 116 mv oc input current (oc = 100mv) C50 C100 na default blanking time comp = 2.5v, fb = 1v, r blank = 40k (note 10) 180 ns adjustable blanking time comp = 2.5v, fb = 1v, r blank = 120k 540 ns v blank 1 v sout driver sout clamp voltage i (gate) = 0a, comp = 2.5v, fb = 1v 10.5 12 13.5 v sout low level i (gate) = 25ma 0.5 0.75 v sout high level i (gate) = C25ma, v in = 12v, comp = 2.5v, fb = 1v 10 v sout active pull-off in shutdown v in = 5v, sd_v sec = 0v, sout = 1v 1 ma sout to out (rise) delay (t delay ) comp = 2.5v, fb = 1v (note 10) r delay = 120k 40 120 ns ns v delay 0.9 v out driver out rise time fb = 1v, cl = 1nf (notes 3, 6) 50 ns out fall time fb = 1v, cl = 1nf (notes 3, 6) 30 ns out clamp voltage i (gate) = 0a, comp = 2.5v, fb = 1v 11.5 13 14.5 v out low level i (gate) = 20ma i (gate) = 200ma 0.45 1.25 0.75 1.8 v v out high level i (gate) = C20ma, v in = 12v, comp = 2.5v, fb = 1v i (gate) = C200ma, v in = 12v, comp = 2.5v, fb = 1v 9.9 9.75 v v out active pull-off in shutdown v in = 5v, sd_v sec = 0v, out = 1v 20 ma out max duty cycle comp = 2.5v, fb = 1v, r delay = 10k (f osc = 200khz), v in = 10v sd_v sec = 1.4v, ss_maxdc = v ref 83 90 % out max duty cycle clamp comp = 2.5v, fb = 1v, r delay = 10k (f osc = 200khz), v in = 10v sd_v sec = 1.32v, ss_maxdc = 1.84v sd_v sec = 2.64v, ss_maxdc = 1.84v 63.5 25 72 33 80.5 41 % % the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c (note 2). comp = open, fb = 1.4v, r osc = 178k, sync = 0v, ss_maxdc = v ref , v ref = 0.1f, sd_v sec = 2v, blank = 121k, delay = 121k, i sense = 0v, oc = 0v, out = 1nf, v in = 15v, sout = open, unless otherwise specifed. electrical characteristics
lt1952/lt1952-1 5 19521fe note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1952/lt1952-1 are tested under pulsed load conditions such that t j t a . the lt1952egn/lt1952egn-1 are guaranteed to meet performance specifcations from 0c to 125c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt1952ign/lt1952ign-1 are guaranteed over the C40c to 125c operating junction temperature range and the lt1952mpgn/lt1952mpgn-1 are tested and guaranteed over the full C55c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifcations is determined by specifc operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: rise and fall times are measured at 10% and 90% levels. note 4: guaranteed by correlation to static test. note 5: each ic includes over-temperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when over-temperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 6: guaranteed but not tested. note 7: maximum recommended sync frequency = 500khz. note 8: in applications where the v in pin is supplied via an external rc network from a system v in > 25v, an external zener with clamp voltage v in on(max) < v z < 25v should be connected from the v in pin to ground. note 9: v in start-up current is measured at v in = v in on C 0.25v and scaled by x 1.18 (to correlate to worst case v in start-up current at v in on ). note 10: timing for r = 40k derived from measurement with r = 240k. the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c (note 2). comp = open, fb = 1.4v, r osc = 178k, sync = 0v, ss_maxdc = v ref , v ref = 0.1f, sd_v sec = 2v, blank = 121k, delay = 121k, i sense = 0v, oc = 0v, out = 1nf, v in = 15v, sout = open, unless otherwise specifed. electrical characteristics parameter conditions min typ max units soft-start ss_maxdc low level: v ol i (ss_maxdc) = 150a, oc = 1v 0.2 v ss_maxdc soft-start reset threshold measured on ss_maxdc 0.45 v ss_maxdc active threshold fb = 1v, dc > 0% 0.8 v ss_maxdc input current (soft-start pull-down: idis) ss_maxdc = 1v, sd_v sec = 1.4v, oc = 1v 800 a
lt1952/lt1952-1 6 19521fe typical performance characteristics temperature (c) ?50 1.20 fb voltage (v) 1.22 1.25 0 50 75 1952 g01 1.21 1.24 1.23 ?25 25 100 125 temperature (c) ?50 155 switching frequency (khz) 185 245 0 50 75 1952 g02 170 230 215 200 ?25 25 100 125 temperature (c) ?50 100 v in shutdown current (a) 200 500 0 50 75 1952 g03 150 400 300 450 350 250 ?25 25 100 125 v in = 15v sd_v sec = 0v temperature (c) ?50 v in startup current (a) 200 500 0 50 75 1952 g04 400 300 450 600 550 350 250 ?25 25 100 125 sd_v sec = 1.4v lt1952 lt1952-1 temperature (c) ?50 3.5 v in i q (ma) 4.5 6.5 0 50 75 1952 g05 4.0 6.0 5.5 5.0 ?25 25 100 125 oc = open temperature (c) ?50 1.22 sd_v sec turn on threshold (v) 1.27 1.42 0 50 75 1952 g06 1.37 1.32 ?25 25 100 125 temperature (c) ?50 0 sd_v sec pin current (a) 15 0 50 75 1952 g07 10 5 ?25 25 100 125 0ma pin current after part turn on pin current before part turn on temperature (c) ?50 6 8 v in (v) 18 16 14 12 0 50 75 1952 g08 10 ?25 25 100 125 lt1952 v in turn off voltage lt1952-1 v in on lt1952-1 v in off lt1952 v in turn on voltage temperature (c) ?50 0 comp (v) 0.4 1.6 1.4 1.2 0 50 75 1952 g09 0.2 1.0 0.8 0.6 ?25 25 100 125 r isense = 0k v in start-up current vs temperature v in i q vs temperature sd_v sec turn on threshold vs temperature sd_v sec pin current vs temperature v in turn on/off voltage vs temperature comp active threshold vs temperature fb voltage vs temperature switching frequency vs temperature v in shutdown current vs temperature
lt1952/lt1952-1 7 19521fe typical performance characteristics temperature (c) ?50 5.0 comp source current (ma) ? (C1) 12.5 0 50 75 1952 g10 10.0 7.5 C25 25 100 125 current out of pin fb = 1v comp = 1.6v temperature (c) ?50 5.0 comp sink current (ma) 12.5 0 50 75 1952 g11 10.0 7.5 ?25 25 100 125 fb = 1.4v comp = 1.6v temperature (c) ?50 0 comp pin current (a) 50 40 30 0 50 75 1952 g12 10 20 ?25 25 100 125 fb = v ref comp = 1.6v comp (v) 0 0 i sense max threshold (mv) 240 160 200 120 1.0 2.0 2.5 1952 g13 40 80 0.5 1.5 3.0 t a = 25c r isense = 0k oc threshold temperature (c) ?50 200 i sense max threshold (mv) 210 240 0 50 75 1952 g14 230 220 ?25 25 100 125 comp = 2.5v r isense = 0k duty cycle (%) 0 0 i sense pin current (a) 10 40 20 50 60 1952 g15 30 20 10 30 40 80 70 90 100 t a = 25c duty cycle (%) 0 175 185 i sense max threshold (mv) 195 225 20 50 60 1952 g16 215 205 10 30 40 80 70 90 100 r slope = 1k r slope = 470w r slope = 0w t a = 25c comp = 2.5v temperature (c) ?50 80 oc threshold (mv) 90 120 0 50 75 1952 g17 110 100 ?25 25 100 125 precision overcurrent threshold independent of duty cycle temperature (c) ?50 0 blank duration (ns) 200 800 0 50 75 1952 g18 600 400 ?25 25 100 125 r blank = 40k r blank = 120k i sense maximum threshold vs comp i sense maximum threshold vs temperature i sense pin current (out of pin) vs duty cycle i sense maximum threshold vs duty cycle (programming slope compensation) oc (overcurrent) threshold vs temperature blank duration vs temperature comp source current vs temperature comp sink current vs temperature (disabled) comp pin current vs temperature
lt1952/lt1952-1 8 19521fe r blank (k) 0 0 blank (ns) 400 200 1000 40 80 100 1952 g26 800 600 20 60 140120 160 t a = 25c temperature (c) ?50 0 t delay (ns) 50 200 0 50 75 1952 g19 150 100 ?25 25 100 125 r delay = 40k r delay = 120k r delay (k) 0 0 t delay (ns) 80 240 80 160 200 1952 g27 160 40 120 240 t a = 25c out load capacitance (pf) 0 0 out rise/fall time (ns) 50 25 125 2000 3000 100 75 1000 4000 5000 t r t f 1952 g20 t a = 25c f osc (khz) 100 70 out duty cycle (%) 80 100 200 300 90 400 500 1952 g21 t a = 25c ss_maxdc = 2.5v sd_v sec = 1.4v sd_v sec (v) 1.32 0 70 out max duty cycle clamp (%) 80 90 1.65 1.98 60 50 40 30 20 10 2.31 2.64 1952 g22 t a = 25c ss_maxdc = 1.84v f osc = 200khz r delay = 10k ss_maxdc (v) 1.60 20 70 out max duty cycle clamp (%) 80 90 1.84 2.08 60 50 40 30 1952 g23 t a = 25c f osc = 200khz r delay = 10k sd_v sec = 1.32v sd_v sec = 1.98v sd_v sec = 2.64v f osc (khz) 100 1.60 2.08 ss_maxdc (v) 2.20 2.32 500 400 300 200 1.96 1.84 1.72 1952 g24 t a = 25c sd_v sec = 1.32v r delay = 10k 0 0.8 ss_maxdc (mv) 1.0 1.2 0.6 0.4 0.2 1952 g25 temperature (c) ?50 0 50 75 ?25 25 100 125 active threshold reset threshold typical performance characteristics out rf t out l c out m d c osc out m d c clamp sd sec out m d c clamp ssmaxdc ssmaxdc s osc out dc ssmaxdc r a t t blank d r blank delay sout r out r t delay sout r out r r delay
lt1952/lt1952-1 9 19521fe pin functions comp (pin 1): output pin of the error amplifer. the error amplifer is an op amp, allowing various compensation networks to be connected between the comp pin and fb pin for optimum transient response. the voltage on this pin corresponds to the peak current of the external fet. full operating voltage range is between 0.8v and 2.5v corresponding to 0mv to 220mv at the i sense pin. for applications using the 100mv oc pin for overcurrent detection, typical operating range for the comp pin is 0.8v to 1.6v. for isolated applications where comp is controlled by an opto-coupler, the comp pin output drive can be disabled with fb = v ref , reducing the comp pin current to (comp C 0.7)/40k. fb (pin 2): monitors the output voltage via an external resistor divider and is compared with an internal 1.23v reference by the error amplifer. fb connected to v ref disables error amplifer output. r osc (pin 3): a resistor to ground programs the operating frequency of the ic between 100khz and 500khz. nominal voltage on the r osc pin is 1.0v. sync (pin 4): used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. if unused, the pin can be left open or connected to ground. ss_maxdc (pin 5): external resistor divider from v ref sets maximum duty cycle clamp (ss_maxdc = 1.84v, sd_v sec = 1.32v gives 72% duty cycle). capacitor on ss_maxdc pin in combination with external resistor divider sets soft-start timing. v ref (pin 6): the output of an internal 2.5v reference which supplies control circuitry in the ic. capable of sourcing up to 2.5ma drive for external use. bypass to ground with a 0.1f ceramic capacitor. sd_v sec (pin 7): the sd_v sec pin, when pulled below its accurate 1.32v threshold, is used to turn off the ic and reduce current drain from v in . the sd_v sec pin is connected to system input voltage through a resistor divider to defne undervoltage lockout (uvlo) and to provide a volt-second clamp on the out pin. a 10a pin current hysteresis allows external programming of uvlo hysteresis. gnd (pin 8): analog ground. blank (pin 9): a resistor to ground adjusts the extended blanking period of the overcurrent and current sense amplifer outputs during fet turn onto prevent false current limit trip. increasing the resistor value increases the blanking period. i sense (pin 10): the current sense input for the control loop. connect this pin to the sense resistor in the source of the external power mosfet. a resistor in series with the i sense pin programs slope compensation. oc (pin 11): an accurate 107mv threshold, independent of duty cycle, for overcurrent detection and trigger of soft-start. connect this pin directly to the sense resistor in the source of the external power mosfet. delay (pin 12): a resistor to ground adjusts the delay period between sout rising edge and out rising edge. used to maximize effciency in forward converter applica - tions by adjusting the control timing of secondary side synchronous rectifer mosfets. increasing the resistor value increases the delay period. pgnd (pin 13): power ground. out (pin 14): drives the gate of an n-channel mosfet between 0v and v in with a maximum limit of 13v on out pin set by an internal clamp. active pull-off exists in shutdown (see electrical specifcation). v in (pin 15): input supply for the part. it must be closely decoupled to ground. an internal undervoltage lockout threshold exists for v in at approximately 14.25v on and 8.75v off for the lt1952. the lt1952-1 has lower undervoltage lockout thresholds set at 7.75v on and 6.5v off. sout (pin 16): switched output in phase with out pin. provides sync signal for control of secondary side fets in forward converter applications requiring highly effcient synchronous rectifcation. sout is actively clamped to 12v. active pull-off exists in shutdown (see electrical specifcation).
lt1952/lt1952-1 10 19521fe timing diagram block diagram 1952 f01 t delay : programmable synchronous delay faults triggering soft-start v in < 8.75v or sd_v sec < 1.32v (uvlo) or oc > 107mv (overcurrent) soft-start latch reset: v in > 14.25v (> 8.75v if latch set by oc) and sd_v sec > 1.32v and oc < 107mv and ss_maxdc < 0.45v soft-start latch set sout out ss_maxdc 0.8v (active threshold) 0.45v (reset threshold) 0.2v v ref >90% ? + ? + + ? source 2.5ma 2.5v 1.23v (100 to 500)khz osc (typical 200khz) i hyst 10a sd_v sec = 1.32v 0a sd_v sec > 1.32v 7 5 14 13 6 3 4 10 8 1 9 2 sd_v sec r osc sync 1.32v 1.23v adaptive maximum duty cycle clamp (linear) slope comp 8a 0% dc 35a 80% dc ramp s q r r q s blank fb comp gnd blank 12 delay v ref 15 v in ss_maxdc soft-start control out 16 sout pgnd i sense 11 oc driver 1a 50ma 12v 13v 0.45v 1952 bd ? + ? + (voltage) error amplifier 107mv 0mv to 220mv on delay v in on v in off lt1952 i start = 460a v in on = 14.25v v in off = 8.75v lt1952-1 i start = 400a v in on = 7.75v v in off = 6.5v start-up input current (istart) ? + + ? sense current + ? over current figure 1. timing diagram figure 2. block diagram
lt1952/lt1952-1 11 19521fe operation introduction the lt1952/lt1952-1 are current mode synchronous pwm controllers optimized for control of the simplest forward converter topology using only one primary mosfet. the lt1952/lt1952-1 are ideal for 25w to 500w power systems where very high effciency and reliability, low complexity and cost are required in a small space. key features of the lt1952/lt1952-1 include an adaptive maximum duty cycle clamp for the single primary mosfet. an additional output signal is included for synchronous rectifer control. a precision 107mv threshold senses overcurrent conditions and triggers soft-start for low stress short-circuit protection and control. the key functions of the lt1952/lt1952-1 are shown in the block diagram in figure 2. part start-up in normal operation the sd_v sec pin must exceed 1.32v and the v in pin must exceed 14.25v (7.75v lt1952-1) to allow the part to turn on. this combination of pin voltages allows the 2.5v v ref pin to become active, supplying the lt1952/lt1952-1 control circuitry and providing up to 2.5ma external drive. sd_v sec threshold can be used for externally programming an undervoltage lockout (uvlo) threshold on the system input voltage. hysteresis on the uvlo threshold can also be programmed since the sd_v sec pin draws 11a just before part turn on and 0a after part turn on. with the lt1952/lt1952-1 turned on, the v in pin can drop as low as 8.75v (6.5v lt1952-1) before part shutdown occurs. this v in pin hysteresis (5.5v lt1952; 1.25v lt1952-1) combined with low 460a (400a lt1952-1) start-up input current allows low power start-up using a resistor/capacitor network from system v in to supply the v in pin (figure 3). the v in capacitor value is chosen to prevent v in falling below its turn off threshold before an auxiliary winding in the converter takes over supply to the v in pin. output drivers the lt1952/lt1952-1 have two outputs, sout and out. the out pin provides a 1a peak mosfet gate drive clamped to 13v. the sout pin has a 50ma peak drive clamped to 12v and provides sync signal timing for syn - chronous rectifcation control. for sout and out turn on, a pwm latch is set at the start of each main oscillator cycle. out turn on is delayed from sout turn on by a time t delay (figure 2). t delay is pro- grammed using a resistor from the delay pin to ground and is used to set the timing control of the secondary synchronous rectifers for optimum effciency. sout and out turn off at the same time each cycle by one of three methods: (1) mosfet peak current sense at i sense pin (2) adaptive maximum duty cycle clamp reached during load/line transients (3) maximum duty cycle reset of the pwm latch during any of the following conditions low v in , low sd_v sec or overcurrent detection at the oc pin a soft- start event is latched and both sout and out turn off immediately (figure 1). leading edge blanking to prevent mosfet switching noise causing premature turn off of sout or out, programmable leading edge blanking exists. this means both the current sense comparator and overcurrent comparator outputs are ignored during mosfet turn on and for an extended period after the out leading edge (figure 6). the extended blanking period is programmable by adjusting a resistor from the blank pin to ground. adaptive maximum duty cycle clamp (volt-second clamp) for forward converter applications using the simplest topology of a single mosfet on the primary, a maximum switch duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the mosfet. this volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. instantaneous load changes can cause the converter loop to demand maximum duty cycle. if the maximum duty cycle of the switch is too great, the transformer reset voltage can exceed the voltage rating of the primary-side mosfet with
lt1952/lt1952-1 12 19521fe operation catastrophic damage. many converters solve this problem by limiting the operational duty cycle of the mosfet to 50% or lessor by using a fxed (non-adaptive) maximum duty cycle clamp with very large voltage rated mosfets. the lt1952/lt1952-1 provide a volt-second clamp to allow mosfet duty cycles well above 50%. this gives greater power utilization for the mosfet, rectifers and transformer resulting in less space for a given power output. in addition, the volt-second clamp allows a reduced voltage rating on the mosfet resulting in lower rds on for greater effciency. the volt-second clamp defnes a maximum duty cycle guard rail which falls when system input voltage increases. the lt1952/lt1952-1 sd_v sec and ss_maxdc pins provide a capacitorless, programmable volt-second clamp solution. some controllers with volt-second clamps control switch maximum duty cycle by using an external capacitor to program maximum switch on time. such techniques have a volt-second clamp inaccuracy directly related to the error of the external capacitor/pin capacitance and the error/drift of the internal oscillator. the lt1952/lt1952- 1 use simple resistor ratios to implement a volt-second clamp without the need for an accurate external capacitor and with an order of magnitude less dependency on oscillator error. an increase of voltage at the sd_v sec pin causes the maximum duty cycle clamp to decrease. if sd_v sec is resistively divided down from transformer input voltage, a volt-second clamp is realised. to adjust the initial maximum duty cycle clamp, the ss_maxdc pin voltage is programmed by a resistor divider from the 2.5v v ref pin to ground. an increase of programmed voltage on ss_maxdc pin provides an increase of switch maximum duty cycle clamp. soft-start the lt1952/lt1952-1 provide true pwm soft-start by using the ss_maxdc pin to control soft-start timing. the proportional relationship between ss_maxdc voltage and switch maximum duty cycle clamp allows the ss_maxdc pin to slowly ramp output voltage by ramping the maximum switch duty cycle clampuntil switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. a soft-start event is triggered whenever v in is too low, sd_v sec is too low (uvlo), or a 107mv overcurrent threshold at oc pin is exceeded. whenever a soft-start event is triggered, switching at sout and out is stopped immediately. the ss_maxdc pin is discharged and only released for charging when it has fallen below its reset threshold of 0.45v and all faults have been removed. increasing voltage on the ss_maxdc pin above 0.8v will increase switch maximum duty cycle. a capacitor to ground on the ss_maxdc pin in combination with a resistor divider from v ref , defnes the soft-start timing. current mode topology (i sense pin) the lt1952/lt1952-1 current mode topology eases fre - quency compensation requirements because the output inductor does not contribute to phase delay in the regulator loop. this current mode technique means that the error amplifer (nonisolated applications) or the optocoupler (isolated applications) commands current (rather than voltage) to be delivered to the output. this makes frequency compensation easier and provides faster loop response to output load transients. a resistor divider from the applications output voltage generates a voltage at the inverting fb input of the lt1952/ lt1952-1 error amplifer (or to the input of an external optocoupler) and is compared to an accurate reference (1.23v for lt1952/lt1952-1). the error amplifer output (comp) defnes the input threshold (i sense ) of the current sense comparator. comp voltages between 0.8v (active threshold) and 2.5v defne a maximum i sense threshold from 0mv to 220mv. by connecting i sense to a sense resistor in series with the source of an external power mosfet, the mosfet peak current trip point (turn off) can be controlled by comp level and hence by the output voltage. an increase in output load current causing the output voltage to fall, will cause comp to rise, increasing i sense threshold, increasing the current delivered to the output. for isolated applications, the error amplifer comp output can be disabled to allow the optocoupler to take control. setting fb = v ref disables the error amplifer comp output, reducing pin current to (comp C 0.7)/40k.
lt1952/lt1952-1 13 19521fe shutdown and programming undervoltage lockout the lt1952/lt1952-1 have an accurate 1.32v shutdown threshold at the sd_v sec pin. this threshold can be used in conjunction with a resistor divider to defne the undervoltage lockout threshold (uvlo) of the system input voltage (v s ) to the power converter (figure 3). a pin current hysteresis (10a before part turn on, 0a after part turn on) allows uvlo hysteresis to be programmed. calculation of the on/off thresholds for the supply (sv in ) to the power converter can be made as follows: v s off threshold = 1.32[1 + (r1/r2)] v s on threshold = sv in off + (10a ? r1) a simple open drain transistor can be added to the resistor divider network at the sd_v sec pin to control the turn off of the lt1952/lt1952-1 (figure 3). the sd_v sec pin must not be left open since there must be an external source current >10a to lift the pin past its 1.32v threshold for part turn on. applications information micropower start-up: selection of start-up resistor and capacitor for v in the lt1952/lt1952-1 use turn-on voltage hysteresis at the v in pin and low start-up current to allow micro-power start-up (figure 4). the lt1952/lt1952-1 monitor v in pin voltage to allow part turn on at 14.25v (7.75v lt1952-1) and part turn off at 8.75v (6.5v lt1952-1). low start-up operation slope compensation the current mode architecture requires slope compensa - tion to be added to the current sensing loop to prevent subharmonic oscillations which can occur for duty cycles above 50%. unlike most current mode converters which have a slope compensation ramp that is fxed internally, placing a constraint on inductor value and operating frequency, the lt1952/lt1952-1 have externally adjust - able slope compensation. slope compensation can be programmed by inserting an external resistor (r slope ) in series with the i sense pin. the lt1952/lt1952-1 have a linear slope compensation ramp which sources current out of the i sense pin of approximately 8a at 0% duty cycle to 35a at 80% duty cycle. overcurrent detection and soft-start (oc pin) an added feature to the lt1952/lt1952-1 is a precise 100mv sense threshold at the oc pin used to detect overcurrent conditions in the converter and set a soft-start latch. the oc pin is connected directly to the source of the primary side mosfet to monitor peak current in the mosfet (figure 7). the 107mv threshold is constant over the entire duty cycle range of the converter because it is unaffected by the slope compensation added to the i sense pin. synchronizing a sync pin allows the lt1952/lt1952-1 oscillator to be synchronized to an external clock. the sync pin can be driven from a logic level output, requiring less than 0.8v for a logic level low and greater than 2.2v for a logic level high. duty cycle should run between 10% and 90%. to avoid loss of slope compensation during synchroniza - tion, the free running oscillator frequency (f osc ) should be programmed to 80% of the external clock frequency (f sync ). the r slope resistor chosen for non-synchronized operation should be increased by 1.25x (= f sync /f osc ). figure 3. programming undervoltage lockout (uvlo) 1.32v system input (v s ) optional shutdown transistor 1952 f03 sd_v sec 11a lt1952/lt1952-1 r1 r2 + ? offon
lt1952/lt1952-1 14 19521fe current (460a lt1952; 400a lt1952-1) allows a large resistor to be connected between system input supply and v in . once the part is turned on, input current increases to drive the ic (4.5ma) and the output drivers (i drive ). a large enough capacitor is chosen at the v in pin to prevent v in falling below its turn off threshold before an auxiliary winding in the converter takes over supply to v in . this technique allows a simple resistor/capacitor for start-up which draws low power from the system supply to the converter. the values for r start and c start are given by: r start(max) = (v s(min) C v in on(max) )/i start(max) c start(min) = (i q(max) + i drive(max) ) ? t start / v in hyst(min) example: (lt1952) for v s(min) = 36v, v in on(max) = 15.75v, i start(max) = 700a, i q(max) = 5.5ma, i drive(max) = 5ma, v in hyst(min) = 3.75v and t start = 100s, r start = (36 C 15.75)/700a = 28.9k (choose 28.7k) c start = (5.5ma + 5ma) ? 100s/3.75v = 0.28f (typically choose 1f) for system input voltages exceeding the absolute maximum rating of the lt1952/lt1952-1 v in pin, an external zener should be connected from the v in pin to ground. this covers the condition where v in charges past v in on but the part does not turn on because sd_v sec < 1.32v. in this condition v in will continue to charge towards system v in , applications information possibly exceeding the rating for the v in pin. the zener voltage should obey v in on(max) < v z < 25v. programming oscillator frequency the oscillator frequency (f osc ) of the lt1952/lt1952-1 is programmed using an external resistor (r osc ) connected between the r osc pin and ground. figure 5 shows typical f osc vs r osc resistor values. the lt1952/lt1952-1 free- running oscillator frequency is programmable in the range of 100khz to 500khz. stray capacitance and potential noise pickup on the r osc pin should be minimized by placing the r osc resistor as close as possible to the r osc pin and keeping the area of the r osc node as small as possible. the ground side of the r osc resistor should be returned directly to the (analog ground) gnd pin. r osc can be calculated by: r osc = 9.125k [(4100k/f osc ) C 1] figure 4. low power start-up 1.32v system input (v s ) from auxiliary winding *for v s > 25v, zener d1 recommended (v in on(max) < v z < 25v) 1952 f04 v in (14.25v on, 8.75v off) lt1952 (7.75v on, 6.5v off) lt1952-1 c start d1* r start + ? figure 5. oscillator frequency (f osc ) vs r osc r osc (k) 50 frequency (khz) 400 1952 f05 100 150 250200 300 350 500 450 400 350 300 250 200 150 100 programming leading edge blank time for pwm controllers driving external mosfets, noise can be generated at the source of the mosfet during gate rise time and some time thereafter. this noise can potentially exceed the oc and i sense pin thresholds of the lt1952/lt1952-1 to cause premature turn off of sout and out in addition to false trigger of soft-start. the lt1952/ lt1952-1 provide programmable leading edge blanking of the oc and i sense comparator outputs to avoid false current sensing during mosfet switching.
lt1952/lt1952-1 15 19521fe blanking is provided in 2 phases (figure 6): the frst phase automatically blanks during gate rise time. gate rise times can vary depending on mosfet type. for this reason the lt1952/lt1952-1 perform true leading edge blanking by automatically blanking oc and i sense comparator outputs until out rises to within 0.5v of v in or reaches its clamp level of 13v. the second phase of blanking starts after the leading edge of out has been completed. this phase is programmable by the user with a resistor connected from the blank pin to ground. typical durations for this portion of the blanking period are from 45ns at r blank = 10k to 540ns at r blank = 120k. blanking duration can be approximated as: blanking (extended) = [45(r blank /10k)]ns (see graph in typical performance characteristics) applications information the mosfet. the current limit for the converter can be programmed by: current limit = (107mv/r s )(n p /n s ) C (1/2)(i ripple ) where: r s = sense resistor in source of primary mosfet i ripple = p-p ripple current in the output inductor l1 n s = number of transformer secondary turns n p = number of transformer primary turns programming slope compensation the lt1952/lt1952-1 use a current mode architecture to provide fast response to load transients and to ease frequency compensation requirements. current mode switching regulators which operate with duty cycles above 50% and have continuous inductor current must add slope compensation to their current sensing loop to prevent subharmonic oscillations. (for more information on slope compensation, see application note 19.) the lt1952/ lt1952-1 have programmable slope compensation to allow a wide range of inductor values, to reduce susceptibility to pcb generated noise and to optimize loop bandwidth. the lt1952/lt1952-1 program slope compensation by inserting a resistor r slope in series with the i sense pin (figure 7). the lt1952/lt1952-1 generate a current at the i sense pin which is linear from 0% duty cycle to the maximum duty cycle of the out pin. a simple calculation of i(i sense ) ? r slope gives an added ramp to the voltage at the i sense pin for programmable slope compensation. (see both graphs i sense pin current vs. duty cycle and i sense maximum threshold vs duty cycle in the typical performance characteristics section.) figure 6. leading edge blank timing r blank (min) = 10k 10k < r blank 240k 100ns (automatic) leading edge blanking (programmable) extended blanking current sense delay out blanking 1952 f06 0 xns x + 45ns [x + 45(r blank /10k)]ns programming current limit (oc pin) the lt1952/lt1952-1 use a precise 107mv sense threshold at the oc pin to detect overcurrent conditions in the converter and set a soft-start latch. it is independent of duty cycle because it is not affected by slope compensation programmed at the i sense pin. the oc pin monitors the peak current in the primary mosfet by sensing the voltage across a sense resistor (r s ) in the source of figure 7. programming slope compensation current slope = 35a ? dc v (isense) = v s + (i sense ? r slope ) i sense = 8a + 35dc a dc = duty cycle for sync operation i sense(sync) = 8a + (k ? 35dc)a k = f osc /f sync 1952 f07 i sense out lt1952/ lt1952-1 oc r s r slope v s
lt1952/lt1952-1 16 19521fe programming synchronous rectifer timing: sout to out delay (t delay ) the lt1952/lt1952-1 have an additional output sout which provides a 50ma peak drive clamped to 12v. in applications requiring synchronous rectifcation for high effciency, the lt1952/lt1952-1 sout provides a sync signal for secondary side control of the synchronous rectifer mosfets (figure 11). timing delays through the converter can cause non-optimum control timing for the synchronous rectifer mosfets. the lt1952/lt1952-1 provide a programmable delay (t delay , figure 8) between sout rising edge and out rising edge to optimize timing control for the synchronous rectifer mosfets to achieve maximum effciency gains. a resistor r delay connected from the delay pin to ground sets the value of t delay . typical values for t delay range from 10ns with r delay = 10k to 160ns with r delay = 160k. (see graph in typical performance characteristics) applications information ss_maxdc pin using a resistor divider from v ref . an increase of voltage at the ss_maxdc pin causes the maximum duty cycle clamp to increase. to program the volt-second clamp, the following steps should be taken: (1)the maximum operational duty cycle of the converter should be calculated for the given application. (2)an initial value for the maximum duty cycle clamp should be calculated using the equation below with a frst pass guess for ss_maxdc. note: since maximum operational duty cycle occurs at minimum system input voltage (uvlo), the voltage at the sd_v sec pin = 1.32v. max duty cycle clamp (out pin) = k ? 0.522(ss_maxdc(dc)/sd_v sec ) C (t delay ? f osc ) where, ss_maxdc(dc) = v ref (r b /(r t + r b ) sd_v sec = 1.32v at minimum system input voltage t delay = programmed delay between sout and out k = 1.11 C 5.5e C7 ? (f osc ) (3) the maximum duty cycle clamp calculated in (2) should be programmed to be 10% greater than the maximum operational duty cycle calculated in (1). simple adjust - ment of maximum duty cycle can be achieved by adjusting ss_maxdc. figure 8. programming sout to out delay: t delay 1952 f08 delay lt1952/ lt1952-1 r delay t delay sout out programming maximum duty cycle clamp for forward converter applications using the simplest topology of a single mosfet on the primary, a maximum switch duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the mosfet. this volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. the lt1952/lt1952-1 sd_v sec and ss_maxdc pins provide a capacitor-less, programmable volt-second clamp solution using simple resistor ratios (figure 9). an increase of voltage at the sd_v sec pin causes the maximum duty cycle clamp to decrease. deriving sd_v sec from a resistor divider connected to system input voltage creates the volt-second clamp. the maximum duty cycle clamp can be adjusted by programming voltage on the figure 9. programming maximum duty cycle clamp system input voltage adaptive duty cycle clamp input max duty cycle clamp adjust input *minimum allowable r t is 10k to guarantee soft-start pull-off 1952 f09 sd_v sec ss_maxdc v ref lt1952/ lt1952-1 r1 r2 r b r t *
lt1952/lt1952-1 17 19521fe example calculation for (2) for r t = 35.7k, r b = 100k, v ref = 2.5v, r delay = 40k, f osc = 200khz and sd_v sec = 1.32v, this gives ss_maxdc(dc) = 1.84v, t delay = 40ns and k = 1 maximum duty cycle clamp = 1 ? 0.522(1.84/1.32) C (40ns ? 200khz) = 0.728 C 0.008 = 0.72 (duty cycle clamp = 72%) note 1: to achieve the same maximum duty cycle clamp at 100khz as calculated for 200khz, the ss_maxdc voltage should be reprogrammed by: ss_maxdc(dc) (100khz) = ss_maxdc(dc) (200khz) ? k (200khz)/k (100khz) = 1.84 ? 1.0/1.055 = 1.74v (k = 1.055 for 100khz) note 2 : to achieve the same maximum duty cycle clamp while synchronizing to an external clock at the sync pin, the ss_maxdc voltage should be re-programmed as: ss_maxdc (dc) (fsync) = ss_maxdc (dc) (200khz) ? [(fosc/fsync) + 0.09(fosc/200khz)0.6] for ss_maxdc (dc) (200khz) = 1.84v for 72% duty cycle ss_maxdc (dc) (fsync = 250khz) for 72% duty cycle = 1.84 ? [(200khz/250khz) + 0.09(1)0.6] = 1.638v programming soft-start timing the lt1952/lt1952-1 have built-in soft-start capability to provide low stress controlled start-up from a list of fault conditions that can occur in the application (see figure 1 and figure 10). the lt1952/lt1952-1 provide true pwm soft-start by using the ss_maxdc pin to control soft-start timing. the proportional relationship between ss_maxdc voltage and switch maximum duty cycle clamp allows the ss_maxdc pin to slowly ramp output voltage by ramping the maximum switch duty cycle clampuntil switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. a capacitor c ss on the ss_maxdc pin and the resistor divider from v ref used to program applications information maximum switch duty cycle clamp, determine soft-start timing (figure 11). a soft-start event is triggered for the following faults: (1) v in < 8.75v, or (2) sd_v sec < 1.32v (uvlo), or (3) oc > 107mv (overcurrent condition) when a soft-start event is triggered, switching at sout and out is stopped immediately. a soft-start latch is set and ss_maxdc pin is discharged. the ss_maxdc pin can only recharge when the soft-start latch has been reset. note: a soft-start event caused by (1) or (2) above, also causes v ref to be disabled and to fall to ground. soft-start latch reset requires all of the following: figure 10. soft-start timing soft-start event triggered timing (a): soft start fault removed before ss_maxdc falls to 0.45v ss_maxdc 0.8v (active threshold) 0.45v (reset threshold) 1952 f10 timing (b): soft-start fault removed after ss_maxdc falls past 0.45v ss_maxdc 0.8v (active threshold) 0.45v (reset threshold) 0.2v figure 11. programming soft-start timing ss_maxdc charging model ss_maxdc(dc) = v ref [r b /(r t + r b )] r charge = [r t ? r b /(r t + r b )] ss_maxdc(dc) 1952 f11 ss_maxdc lt1952/ lt1952-1 r charge ss_maxdc v ref lt1952/ lt1952-1 r b c ss r t c ss 0.8v (active threshold) 0.45v (reset threshold) 0.2v soft-start event triggered timing (a): soft start fault removed before ss_maxdc falls to 0.45v ss_maxdc 0.8v (active threshold) 0.45v (reset threshold) 1952 f10 timing (b): soft-start fault removed after ss_maxdc falls past 0.45v ss_maxdc
lt1952/lt1952-1 18 19521fe (a) v in > 14.25* (7.75v lt1952-1), and (b) sd_v sec > 1.32v, and (c) oc < 107mv, and (d) ss_maxdc < 0.45v (ss_maxdc reset threshold) *v in > 8.75v (6.5v lt1952-1) is ok for latch reset if the latch was only set by overcurrent condition in (3) above. ss_maxdc discharge timing it can be seen in figure 10 that two types of discharge can occur for the ss_maxdc pin. in timing (a) the fault that caused the soft-start event has been removed before ss_maxdc falls to 0.45v. this means the soft-start latch will be reset when ss_maxdc falls to 0.45v and ss_maxdc will begin charging. in timing (b), the fault that caused the soft-start event is not removed until some time after ss_maxdc has fallen past 0.45v. the ss_maxdc pin continues to discharge to 0.2v and remains low until all faults are removed. the time for ss_maxdc to fall to a given voltage can be approximated as: ss_maxdc (t fall ) = (c ss /i dis ) ? [ss_maxdc(dc) C v ss(min) ] where: i dis = net discharge current on c ss c ss = capacitor value at ss_maxdc pin ss_maxdc(dc) = programmed dc voltage v ss(min) = minimum ss_maxdc voltage before recharge i dis ~ 8e C4 + (v ref C v ss(min) )[(1/2r b ) C (1/r t )] for faults arising from (1) and (2), v ref = 100mv. for a fault arising from (3), v ref = 2.5v. ss_maxdc(dc) = v ref [r b /(r t + r b )] v ss(min) = ss_maxdc reset threshold = 0.45v (if fault removed before t fall ) applications information example: for an overcurrent fault (oc > 100mv), v ref = 2.5v, r t = 35.7k, r b = 100k, c ss = 0.1f and assume v ss(min) = 0.45v, i dis ~ 8e C4 + (2.5 C 0.45)[(1/2 ? 100k) C (1/35.7k)] = 8e C4 + (2.05)(C0.23e C4 ) = 7.5e C4 ss_maxdc(dc) = 1.84v ss_maxdc (t fall ) = (1e C 7/7.5e C4 ) ? (1.84 C 0.45) = 1.85eC4 s if the oc fault is not removed before 185s then ss_maxdc will continue to fall past 0.45v towards a new v ss(min) . the typical v ol for ss_maxdc at 150a is 0.2v. ss_maxdc charge timing when all faults are removed and the ss_maxdc pin has fallen to its reset threshold of 0.45v or lower, the ss_maxdc pin will be released and allowed to charge. ss_maxdc will rise until it settles at its programmed dc voltagesetting the maximum switch duty cycle clamp. the calculation of charging time for the ss_maxdc pin between any two voltage levels can be approximated as an rc charging waveform using the model shown in figure 11. the ability to predict ss_maxdc rise time between any two voltages allows prediction of several key timing periods: (1)no switching period (time from ss_maxdc(dc) to v ss(min) + time from v ss(min) to v ss(active) ) (2)converter output rise time (time from v ss(active) to v ss(reg) ; v ss(reg) is the level of ss_maxdc where maximum duty cycle clamp equals the natural duty cycle of the switch) (3)time for maximum duty cycle clamp within x% of target value the time for ss_maxdc to charge to a given voltage v ss is found by re-arranging:
lt1952/lt1952-1 19 19521fe v ss (t) = ss_maxdc(dc) (1 C e (Ct/rc) ) to give: t = rc ? (C1) ? ln(1 C v ss /ss_maxdc(dc)) where: v ss = ss_maxdc voltage at time t ss_maxdc(dc) = programmed dc voltage setting maximum duty cycle clamp = v ref (r b /(r t + r b ) r = r charge (figure 11) = r t ? r b /(r t + r b ) c = c ss (figure 11) example (1) no switching period the period of no switching for the converter, when a soft-start event has occurred, depends on how far ss_maxdc can fall before recharging occurs and how long a fault exists. it will be assumed that a fault triggering soft-start is removed before ss_maxdc can reach its reset threshold (0.45v). no switching period = t discharge + t charge t discharge = discharge time from ss_maxdc(dc) to 0.45v t charge = charge time from 0.45v to v ss(active) t discharge was already calculated earlier as 185s. t charge is calculated by assuming the following: v ref = 2.5v, r t = 35.7k, r b = 100k, c ss = 0.1f and v ss(min) = 0.45v. t charge = t(v ss = 0.8v) C t(v ss = 0.45v) step 1: ss_maxdc(dc) = 2.5[100k/(35.7k + 100k)] = 1.84v r charge = (35.7k ? 100k/135.7k) = 26.3k step 2: t(v ss = 0.45v) is calculated from, t = r charge ? c ss ? (C1) ? ln(1 C v ss /ss_maxdc(dc)) = 2.63e 4 ? 1e C7 ? (C1) ? ln(1 C 0.45/1.84) = 2.63e C3 ? (C1) ? ln(0.755) = 7.3e C4 s applications information step 3: t(v ss = 0.8v) is calculated from: t = r charge ? css ? (C1) ? ln(1 C v ss /ss_maxdc(dc)) = 2.63e4 ? 1e C7 ? (C1) ? ln(1 C 0.8/1.84) = 2.63eC3 ? (C1) ? ln(0.565) = 1.5e C3 s from step 1 and step 2: t charge = (1.5 C 0.73)e C3 s = 7.7e C4 s the total time of no switching for the converter due to a soft-start event: = t discharge + t charge = 1.85e C4 + 7.7e C4 = 9.55e C4 s example (2) converter output rise time the rise time for the converter output to reach regulation can be closely approximated as the time between the start of switching (ss_maxdc = v ss(active) ) and the time where converter duty cycle is in regulation (dc(reg)) and no longer controlled by ss_maxdc (ss_maxdc = v ss(reg) ). converter output rise time can be expressed as: output rise time = t(v ss(reg) ) C t(v ss(active) ) step 1: determine converter duty cycle dc(reg) for output in regulation. the natural duty cycle dc(reg) of the converter depends on several factors. for this example it is assumed that dc(reg) = 60% for system input voltage near the undervoltage lockout threshold (uvlo). this gives sd_v sec = 1.32v. also assume that the maximum duty cycle clamp programmed for this condition is 72% for ss_maxdc(dc) = 1.84v, f osc = 200khz and r delay = 40k. step 2: calculate v ss(reg) to calculate the level of ss_maxdc (v ss(reg) ) that no longer clamps the natural duty cycle of the converter, the equation for maximum duty cycle clamp must be used (see previous section programming maximum duty cycle clamp). the point where the maximum duty cycle clamp meets dc(reg) during soft-start is given by: dc(reg) = max duty cycle clamp 0.6 = k ? 0.522(ss_maxdc(dc)/sd_v sec ) C (t delay ? f osc )
lt1952/lt1952-1 20 19521fe for sd_v sec = 1.32v, fosc = 200khz and r delay = 40k this gives k = 1 and t delay = 40ns. re-arranging the above equation to solve for ss_maxdc = v ss(reg) = [0.6 + (t delay ? f osc )(sd_v sec )]/(k ? 0.522) = [0.6 + (40ns ? 200khz)(1.32v)]/(1 ? 0.522) = (0.608)(1.32)/0.522 = 1.537v step 3: calculate t(v ss(reg) ) C t(v ss(active) ) recall the time for ss_maxdc to charge to a given voltage v ss is given by: t = r charge ? c ss ? (C1) ? ln(1 C v ss /ss_maxdc(dc)) (figure 11 gives the model for ss_maxdc charging) for r t = 35.7k, r b = 100k, r charge = 26.3k for c ss = 0.1f, this gives t(v ss(active) ) = t(v ss(0.8v) ) = 2.63e 4 ? 1e C7 ? (C1) ? ln(1 C 0.8/1.84) = 2.63e C3 ? (C1) ? ln(0.565) = 1.5e C3 s t(v ss(reg) ) = t(v ss(1.537v) ) = 26.3k ? 0.1f ? C1 ? ln(1 C 1.66/1.84) = 2.63e C3 ? (C1) ? ln(0.146) = 5e C3 s the rise time for the converter output = t(v ss(reg) ) C t(v ss(active) ) = (5 C 1.5)e C3 s = 3.5e C3 s example (3) time for maximum duty cycle clamp to reach within x% of target value a maximum duty cycle clamp of 72% was calculated previously in the section programming maximum duty cycle clamp. the programmed value used for ss_maxdc(dc) was 1.84v. the time for ss_maxdc to charge from its minimum value v ss(min) to within x% of ss_maxdc(dc) is given by: t(ss_maxdc charge time within x% of target) = t[(1 C (x/100) ? ss_maxdc(dc)] C t(v ss(min) ) for x = 2 and v ss(min) = 0.45v, t(0.98 ? 1.84) C t(0.45) = t(1.803) C t(0.45) from previous calculations, t(0.45) = 7.3e C 4 s. using previous values for r t , r b , and c ss , applications information t(1.803) = 2.63e C4 ? 1e C7 ? (C1) ? ln(1 C 1.803/1.84) = 2.63e C3 ? (C1) ? ln(0.02) = 1.03e C2 s hence the time for ss_maxdc to charge from its minimum reset threshold of 0.45v to within 2% of its target value is given by: t(1.803) C t(0.45) = 1.03e C2 C 7.3e C4 = 9.57e C3 forward converter applications the following section covers applications where the lt1952/lt1952-1 are used in conjunction with other ltc parts to provide highly effcient power converters using the single switch forward converter topology. 95% effcient, 5v, synchronous forward converter the circuit in figure 14 is based on the lt1952-1 to provide the simplest forward power converter circuitusing only one primary mosfet. the sout pin of the lt1952-1 provides a synchronous control signal for the ltc1698 located on the secondary. the ltc1698 drives secondary side synchronous rectifer mosfets to achieve high effciency. the ltc1698 also serves as an error amplifer and optocoupler driver. effciency and transient response are shown in figures 12 and 13. peak effciencies of 95% and ultra-fast transient response are superior to presently available power modules. integrated soft-start, overcurrent detection and short-circuit hiccup mode provide low stress, reliable protection. in addition, the circuit in figure 14 is an all- ceramic capacitor solution providing low output ripple voltage and improved reliability. the lt1952-based converter can be used to replace power module converters at a much lower cost. the lt1952 solution benefts from thermal conduction of the system board resulting in higher effciencies and lower rise in component temperatures. the 7mm height allows dense packaging and the circuit can easily be adjusted to provide an output voltage from 1.23v to 26v. higher currents are achievable by simple scaling of power components. the lt1952-1-based solution in figure 14 is a powerful topology for replacement of a wide range of power modules.
lt1952/lt1952-1 21 19521fe applications information load current (a) 0 efficiency (%) 2520 1952 f12 5 10 15 98 96 94 92 90 88 86 v in = 48v v out = 5v f osc = 300khz figure 12. lt1952-based synchronous forward converter effciency vs load current (for circuit in figure 14) figure 14. 36v to 72v input to 5v at 20a synchronous forward converter v dd cg pgnd gnd opto v comp v fb fg sync v aux i comp +i sns ?i sns ovp ltc1698 1 2 3 4 5 6 8 16 15 14 13 12 11 9 hcpl-m453 0.1f 10v bias 6 5 4 1 2 3 sync 7v bias +v 0ut r14 1.2k r16 12.4k r15 38.3k c9, 6.8nf 1f x5r r13 270 0.1f t1 pa0491 q2 ph3830 q3 ph3830 l1 pa1393.152 c 01 100f x5r 2 +v 0ut 5v 20a sync 220pf 560 t2 sout sout c in 2.2f 100v x5r +v in 36v to 72v 1952 f14 q1: phm15nq20 philips sd_v sec out oc i sense pgnd gnd v in lt1952-1 blank delay 9 12 16 5 6 2 3 4 7 14 11 10 13 8 15 115k 1k 0.1f 0.1f 10v bias 475k 18.2k 22k 40k 33k 4.75k 9.53k 100k q1 0.015 comp 1 1f sync sout ss_maxdc v ref fb r osc v out (200mv/div) 0a i out (5a/div) 20s/div 1952 f13 figure 13. output voltage transient response (6a to 12a load step at 6a/s)
lt1952/lt1952-1 22 19521fe 48v to isolated 12v, 20a (no opto-coupler) bus converter the wide programmable range and accuracy of the lt1952/lt1952-1 volt-second clamp makes the lt1952/ lt1952 - 1 an ideal choice for bus converter applications where the volt-second clamp provides line regulation for the converter output. the 48v to 12v 20a bus converter application in figure16 shows a semi-regulated isolated output without the need for an optocoupler, optocoupler driver, reference or feedback network. some bus converter solutions run with a fxed 50% duty cycle resulting in an output variation of 2-to-1 for applications with a 72v to 36v input range. the lt1952/lt1952-1 use an accurate wide programmable range volt-second clamp to initially program and then control power supply output voltage to typically 10% for the same 36v to 72v input range. effciency for the lt1952 based bus converter in figure 16 applications information achieves a high 94% at 20a (figure 15). the solution is only slightly larger than 1/4 brick size and uses only ceramic capacitors for high reliability. load current (a) 4 efficiency (%) 96.0 95.5 95.0 94.5 94.0 93.5 93.0 10 12 14 86 16 18 20 1952 f15 v in = 48v v out = 12v figure 15. lt1952-based synchronous bus converter effciency vs load current (for circuit in figure 16) figure 16. 36v to 72v input to 12v at 20a no optocoupler synchronous bus converter ? ?? ?? ltc3900 8v bias v u1 v u1 220pf 8v bias 3 fg 5 cg v in 36v to 72v t1 pa0815.002 bas516 bcx55 v out 12v, 20a 10k 10k 10k c t 1nf 1f r t 15k 560w l1: pa1494.242 pulse engineering t1: pulse engineering t2: coilcraft c out 33f, 16v x5r, tdk 3x 0.1f 2.2f, 100v 2x 1nf bat760 12v si7370 2x ph4840 2x 18v t2 q4470-b 82k 47k 1952 f16 2.4h sd_v sec out lt1952 7 14 r osc v in 3 15 blank gnd 9 8 ss_maxdc pgnd 5 13 delay 12 v ref oc 6 11 comp i sense 1 10 fb sout 2 16 ? ph21nq15 2x 1 gnd 6 cs + 2 v cc 4 cs ? 7 sync 8 timer 370k 9m 1f 470 39k 13.2k 115k 27k 0.47f 0.1f 10k59k
lt1952/lt1952-1 23 19521fe 36v to 72v input, 3.3v 40a converter an lt1952-based synchronous forward converter provides the ideal solution for power supplies requiring high effciency at low output voltages and high load currents. the 3.3v 40a solution in figure 18 achieves peak effciencies of 92.5% (figure 17) by minimizing power loss due to rectifcation at the output. synchronous rectifer control output sout, with programmable delay, optimizes timing control for a secondary side synchronous mosfet controller (ltc3900) which results in high effciency synchronous rectifcation. the lt1952/lt1952-1 use a precision current limit threshold at the oc pin combined with a soft-start hiccup mode to provide low stress output short-circuit protection. the maximum output current will vary only 10% over the full v in range. during short-circuit the average power dissipation of the circuit will be lower than 15% of maximum rated power thanks to a soft-start controlled hiccup mode. applications information this allows a signifcant reduction in power component sizing using the lt1952-based converter. output current (a) 0 10 efficiency (%) 50 1952 f17 20 30 40 94 93 92 91 90 89 88 87 86 v in = 48v v out = 3.3v f osc = 300khz figure 17. lt1952-based synchronous forward converter effciency vs load current (for circuit in figure 18) figure 18. 36v to 72v, 3.3v at 40a synchronous forward converter ? ?? ?? ltc3900 8v bias v u1 v u1 220pf bat760 8v bias 3 fg 5 cg +v in 36v to 72v pa0912.002 bas516 bcx55 v out 3.3v, 40a 10k 10k 10k 1nf 8v bias 1mf 15k 560 c out 100f 3x 0.1f 2.2mf 1nf 12v q2 ph3230 2x q3 ph3230 2x + ? 18v 270 ps2801 t2 q4470-b 2.2nf v u1 18k 249k 80.6k 1f 0.1f 10k 10k 82k 47k 4 3 5 4 8 2 1 lt1009 lt1797 1952 f18 l1 sd_v sec out lt1952 7 14 r osc v in 3 15 blank gnd 9 8 ss_maxdc pgnd 5 13 delay 12 v r = 2.5v oc 6 11 comp i sense 1 10 fb = 1.23v sout 2 16 ? si7846 1 gnd 6 cs + 2 v cc 4 cs ? 7 sync 8 timer 370k 10m 1f 470 39k 13.2k 115k 27k 0.22f 0.1f 10k59k 33k 2.2k 22k l1: pa0713, pulse engineering all capacitors x7r, ceramic, tdk t2: coilcraft
lt1952/lt1952-1 24 19521fe bus converter: optimum output voltage tolerance the bus converter applications shown on page 1 and in figure 16, provide semi-regulated isolated outputs without the need for an optocoupler, optocoupler driver, reference or feedback network. the lt1952/lt1952-1volt-second clamp adjusts switch duty cycle inversely proportional to input voltage to provide an output voltage that is regulated against input line variations. some bus converters use a switch duty cycle limit which causes output voltage variation of typically 33% over a 2:1 input voltage range. the lt1952/lt1952-1 typically provide a 10% output variation for the same input variation. typical output tolerance is further improved for the lt1952 by inserting a resistor from the system input voltage to the ss_maxdc pin (rx in figure 19). the lt1952/lt1952-1 electrical specifcations for the out max duty cycle clamp show typical switch duty cycle to move from 72% to 33% for a 2x change of input voltage (ss_maxdc pin = 1.84v). since output voltage regulation follows v in ? duty cycle, a switch duty cycle change of 72% to 36% (for a 2x input voltage change) provides minimal output voltage variation for the lt1952/lt1952-1 bus converter. to achieve this, an ss_maxdc pin voltage increase of 1.09x (36/33) would be required at high input line. a resistor rx inserted between the ss_maxdc pin and system input voltage (figure 19) increases ss_maxdc voltage as input voltage increases, minimizing output voltage variation over a 2:1 input voltage change. the following steps determine values for rx, r t and r b : (1)program switch duty cycle at minimum system input voltage (v s(min) ) (a)r t(1) = 10k (minimum allowed to still guarantee soft- start pull-down) applications information (b)select switch duty cycle for the bus converter for a given output voltage at v s(min) and calculate ss_maxdc voltage (ss1) (see applications information program - ming maximum duty cycle clamp) (c)calculate r b(1) = [ss1/(2.5 C ss1)] ? r t(1) (2)calculate rx: rx = ([v s(max) C v s(min) ]/[ss1 ? (x C 1)]) ? r thev(1) r thev(1) = r b(1) ? r t(1) /(r b(1) + r t(1) ), x = ideal duty cycle (v s(max) )/actual duty cycle (v s(max) ) (3)the addition of rx causes an increase in the original programmed ss_maxdc voltage ss1. a new value for r b(1) should be calculated to provide a lower ss_maxdc voltage (ss2) to correct for this offset: (a)ss2 = ss1 C [(v s(min) C ss1) ? r thev(1) /rx] (b)r b(2) = [ss2/(2.5 C ss2)] ? r t(1) (4)the thevinin resistance r thev(1) used to calculate rx should be re-established for r t and r b : (a) r b (fnal value) = r b(2) ? (r thev(1) /r thev(2) ) (b) r t (fnal value) = r t(1) ? (r thev(1) /r thev(2) ) where r thev(2) = r b(2) ? r t(1) /(r b(2) + r t(1) ) example: for a bus converter running from 36v to 72v input, v s(min) = 36v, v s(max) = 72v. choose r t(1) = 10k, ss_maxdc = ss1 = 1.84v (for 72% duty cycle at v s(min ) = 36v) r b(1) = [1.84v/(2.5v C 1.84v)] ? 10k = 28k r thev(1) = [28k ? 10k/(28k + 10k)] = 7.4k ss_maxdc correction = 36%/33% = 1.09 rx = [(72v C 36v)/(1.84 ? 0.09)] ? 7.4k = 1.6m ss2 = 1.84 C [(36v C 1.84) ? 7.4k/1.6m] = 1.682v r b(2) = [1.682/(2.5 C 1.682)] ? 10k = 20.6k r thev(2) = [20.6k ? 10k/(20.6k + 10k)] = 6.7k r thev(1) /r thev(2) = 7.4k/6.7k = 1.104 r b (fnal value) = 20.6k ? 1.104 = 22.7k (choose 22.6k) r t (fnal value) = 10k ? 1.104 = 11k system input voltage volt-second clamp input volt-second clamp adjust input 1952 f19 sd_v sec ss_maxdc v ref lt1952/ lt1952-1 r1 rx r2 r b r t figure 19. optimal programming of maximum duty cycle clamp for bus converter applications (adding rx)
lt1952/lt1952-1 25 19521fe typical applications v ul v ul lt4430 c19 1f x5r c15 2.2nf 2kv c24 22pf +v ol r38 18.2k 1952 ta02a c17 15nf c16 0.22f 10v r27 470 r17 560 r34 12.1k r35 348k r31 10 r20 115k r3 442 r csl 0.006 r5 10 ltc4440-5 d1 bas516 r14 33k r15 115k r13 22k r23 2k r24 68k r2 560k +v r2 +v b v fb v ul d29 pmeg3002 r32 187k r28 309k r30 1.2k c23 1f c14 1f c10 100pf c8 100pf c21 220pf c3 1f c ul 4.7f c9 100pf v fb r26 220 ps2801-1 d11 bas516 r21 10k r19 47.5k d9 pdz10b d5 pdz10b r18 10k r11 47k r1 2.2 d6 bas521 d7 bas521 r16 33k r54 4.7 r10 1k r8 2.2 d2 bas516 d3 bas516 q3 hat2173 c ol 33f x7r c sys 220f 16v apxe q2 hat2266 t1 g45r2-0405.005 c12 470pf c5 0.22f q9 bcx55 220pf 10h pe-68386 fb cg out v cc gnd ss opto comp fb ltc3900 cs + cs ? cg v cc sync timer gnd fb 1 2 3 6 5 4 8 7 6 5 1 2 3 4 lt1952-1 comp fb r osc sync ss_maxdc v ref sd_v sec gnd v cc gnd inp boost tg ts 1 2 3 6 5 4 sout v in out pgnd delay oc i sense blank 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 l3 680h l2 1.5mh v ul +v b +v in +v in 18v to 72v ?v in +v r2 l1 hr-pqa2050-10 ? ? q10 pbss8110 cg +v ol +v out q1 hat2173 fg 7, 8 9, 10, 11 1 6 ?? r22 13.3k q12 bc856t c10 0.1f c13 0.47f d17 bas516 r45 10k l53 10h c33 0.1f q13 si2325 c34 0.22f out c25 10nf c in 2.2f 3 +v in 2, 3 ? 4, 5 d14 bas516 + i out (a) 0 84 efficiency (%) 86 88 90 92 96 2 4 6 8 1952 ta02b 10 12 94 85 87 89 91 95 93 24v input 48v input the 12v output converter fits in a one-eighth brick footprint and has a very high effciency over 18v to 72v input voltage range wide 18v to 72v input, high effciency, 12v at 12a output, active reset forward converter fits in one-eighth brick footprint
lt1952/lt1952-1 26 19521fe typical applications v fb v ul cs lt4430 c19 1f c15 2.2nf 2kv c24 47pf r38 18.2k 1952 ta03a c17 10nf c16 22f d11 bas516 d6 b0540w r27 470 r34 4.75k r8 2.2 r35 82.5k r20 174k r14 33k r45 10k d14 bas516 r cs1 0.015 r54 4.7 c34 0.22f q1 si7430 q13 si2325 r15 115k r13 22k r23 1.2k r24 39k r29 22k +v r2 +v b ss v fb ss r28 442k r33 470k r32 332k r30 1.2k c23 1f c25 10nf r53 200 c33 0.1f c ul 4.7f d10 bat760 c9 100pf cs c13 0.47f r26 220 ps2801-1 r11 82k r1 2.2 r50 2.2 r49 2.2 t1 pa0861.004 d2 bas516 d3 bas516 q3 hat2165 c ol 100f 2 c sys 470f 6.3v q2 hat2165 v cc gnd ss opto comp fb 1 2 3 6 5 4 lt1952-1 comp fb r osc sync ss_maxdc v ref sd_v sec gnd sout v in out pgnd delay oc i sense blank 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 d17 bas516 l2 1.5mh v ul +v b +v in +v in ?v in v r2 d5 pdz10b l1 pa1671.650 q10 pbss8110 +v out 7, 8 9, 10, 11 1 6 ?? r22 13.3k q12 bc856t c10 0.1f c in 2.2f 2 +v in 2, 3 ? 4, 5 + i out (a) 0 88 efficiency (%) 89 90 91 92 93 94 10 20 30 1952 ta03b the high effciency of 3.3v output converter allows tight pcb layout and results in low component temperature rises high effciency 36v to 72v input to 3.3v at 30a output, active reset forward converter fits in one-eighth brick footprint
lt1952/lt1952-1 27 19521fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. rev date description page number e 5/11 mp-grade parts added, changes refected throughout the data sheet 1-28 (revision history begins at rev e)
lt1952/lt1952-1 28 19521fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2004 lt 0511 rev e ? printed in usa package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b) related parts gn16 (ssop) 0204 1 2 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale part number description comments lt c ? 3900 synchronous rectifer n-channel mosfet driver for forward converters programmable timeout and reverse inductor current protection, transformer synchronization, ssop-16 lt4430 secondary-side opto-coupler driver with reference voltage overshoot control prevents output overshoot during start-up and short- circuit recovery ltc3726/ltc3725 isolated synchronous no opto forward controller chip set ideal for medium power 24v or 48v input applications ltc3705/ltc3726 2-switch synchronous forward no opto isolated controller chip set self-starting architecture eliminates need for a bias voltage on primary side ltc3722/ltc2722-2 synchronous isolated full-bridge controllers with zero voltage switching ideal for high power 24v or 48v input applications ltc3723-1/ltc3723-2 synchronous push-pull and full-bridge controllers high effciency with on-chip mosfet drivers ltc3721-1/ltc3721-2 non-synchronous push-pull and full-bridge controllers minimizes external components, on-chip mosfet drivers lt3748 100v no opto flyback controller 5v v in 100v, boundary mode operation, msop-16 with extra high voltage pin spacing ltc3803/ltc3803-3/ ltc3803-5 flyback dc/dc controllers with fixed 200khz or 300khz operating frequency v in and v out limited only by external components, 6-pin thinsot? package

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